Content for TR 45.912 Word version: 18.0.0
12 Adaptation between mobile station receiver diversity and dual-carrier
13 Enhancements to resource allocation
14 Modified MBMS Service
15 Uplink throughput enhancements with low standard impact
A Plots for clause 7 (dual-carrier and multi-carrier)
B Chapter 8 Link simulation results
C Chapter 8 Link simulation results
D Chapter 8 Link simulation results
E Detailed simulation results for reduced transmission time interval (subclause 10.3.2)
F Flow-graphs of SMTP and POP3 scenarios (subclause 10.3.3)
$ Change history
12 Adaptation between mobile station receiver diversity and dual-carrier p. 413
12.1 Introduction p. 413
12.2 Concept description p. 413
12.3 Performance Characterization p. 414
12.4 Impacts to the Mobile Station p. 414
12.5 Impacts to the BSS p. 414
12.6 Impacts to the Core Network p. 414
12.7 Impacts to the Specification p. 414
13 Enhancements to resource allocation p. 415
13.1 Introduction p. 415
13.2 USF and Timeslot Resources p. 417
13.3 Modelling Assumptions and Requirements p. 419
13.3.1 Illustration p. 419
13.4 Performance Characterization p. 423
13.4.1 Cumulative Probability Distribution- MCS-1, QCIF 30 FPS p. 425
13.4.2 Cumulative Probability Distribution- MCS-5, CIF 15 FPS p. 426
13.4.3 Summary of Performance Characterization p. 427
13.5 Discussion: Improvement of B2DA p. 427
13.5.1 Introduction p. 427
13.5.2 Details of proposed allocation scheme p. 428
13.5.3 Benefits of the Solution p. 429
13.6 References p. 429
14 Modified MBMS Service p. 429
14.1 Introduction p. 429
14.2 Concept description p. 430
14.3 Modelling Assumptions and Requirements p. 430
14.4 Receiver Link Performance p. 434
14.5 Radio Resource Management p. 435
14.6 Impacts to the Mobile Station p. 436
14.7 Impacts to the BSS p. 436
14.8 Impacts to the Core Network p. 436
14.9 Impacts to the Specification p. 437
14.10 Open Issues p. 437
14.11 References p. 437
15 Uplink throughput enhancements with low standard impact p. 437
15.1 MS multislot capability switching p. 437
15.1.1 Introduction p. 437
15.1.2 Timeslot allocation p. 437
15.1.3 Full-duplex MS p. 438
15.1.4 Tx power p. 439
15.1.5 Data rate increase p. 439
15.1.6 Data rate increase at the cell edge p. 440
15.1.7 Impacts on mobile stations p. 441
15.1.7.1 Full-duplex MS p. 441
15.1.8 Impacts on the BSS p. 442
15.1.9 Impacts on the core network p. 442
15.1.10 Impacts on the specification p. 442
15.1.11 Summary p. 442
15.2 Type 2 MS Implementation p. 442
15.2.1 Concept Description p. 442
15.2.2 Void
15.2.2a Interference Frequencies p. 443
15.2.2a.1 Introduction and Purpose p. 443
15.2.2a.2 Frequencies of Interest p. 443
15.2.2a.3 Intermodulation Interference p. 444
15.2.2a.3.1 Second Order Intermodulation Term p. 444
15.2.2a.3.2 Third Order Intermodulation Terms p. 444
15.2.2a.4 Intermodulation Frequency Bands p. 445
15.2.2a.5 Cross Modulation Interference p. 447
15.2.2a.6 Summary p. 448
15.2.3 Void
15.2.3a Transmitter Output Power Levels p. 448
15.2.3a.1 No Maximum Output Power Reduction p. 448
15.2.3a.2 No Change in PA Capabilities p. 448
15.2.3a.3 Power Back Off based on Duplexer Power Tolerance p. 449
15.2.4 Void
15.2.4a Analysis Assumptions p. 449
15.2.5 Duplexer and Receive Filter Requirements p. 450
15.2.5.1 Introduction p. 450
15.2.5.2 Methodology p. 450
15.2.5.3 Receiver Bandpass Filter Specifications p. 451
15.2.5.4 Duplexer Filter Specifications p. 452
15.2.5.5 Worst Case Assumption p. 453
15.2.5.6 Filter Specifications p. 453
15.2.5.7 New Duplexer Arrangement for Lower Insertion Loss p. 456
15.2.6 Void
15.2.6a Basic Type 2 Architecture p. 457
15.2.6a.1 Introduction p. 457
15.2.6a.2 Receiver performance p. 457
15.2.6a.3 Mapping Filter Specifications p. 458
15.2.6a.4 Architecture Details p. 458
15.2.6a.4.1 Architecture 1 - The Basic Type 2 Mobile p. 458
15.2.6a.4.2 Architecture 2 - The Basic Type 2 Mobile with Additional Filtering p. 459
15.2.6a.5 Analysis of the Basic Type 2 Architecture p. 460
15.2.6a.5.1 No Maximum Output power Reduction p. 460
15.2.6a.5.2 No Change in PA Capabilities p. 462
15.2.6a.5.3 Power Back Off based on Duplexer Power Tolerance p. 462
15.2.6a.6 Analysis of the Basic Type 2 Architecture with Typical GSM Receiver Filters p. 462
15.2.6a.6.1 No Maximum Output Power Reduction p. 463
15.2.6a.6.2 No Change in PA Capabilities p. 464
15.2.6a.6.3 Power Back Off based on Duplexer Power Tolerance p. 464
15.2.6a.7 Analysis of the Basic Type 2 Architecture with High TX Rejection Receiver Filters p. 465
15.2.6a.7.1 No Maximum Output Power Reduction p. 465
15.2.6a.7.2 No Change in PA Capabilities p. 467
15.2.6a.7.3 Power Back Off based on Duplexer Power Tolerance p. 467
15.2.6a.8 Summary p. 467
15.2.7 Void
15.2.7a Modified Type 2 Architecture p. 468
15.2.7a.1 Introduction p. 468
15.2.7a.2 LNA and Post-Filter Receiver Performance p. 468
15.2.7a.3 Mapping Filter Specifications p. 469
15.2.7a.4 Modified Architecture Details p. 469
15.2.7a.5 Receiver Sensitivity p. 470
15.2.7a.6 Transmitter Output Power Levels p. 471
15.2.7a.7 Analysis Assumptions p. 471
15.2.7a.8 Analysis of the Modified Type 2 Architecture p. 471
15.2.7a.8.1 No Maximum Output power Reduction p. 473
15.2.7a.8.2 No Change in PA Capabilities p. 474
15.2.7a.8.3 Power Back Off based on Duplexer Power Tolerance p. 475
15.2.7a.9 Blocker Power Reduction p. 476
15.2.7a.10 Summary p. 476
15.2.8 Void
15.2.8a Hybrid Type 2 Architecture p. 477
15.2.8a.1 Introduction p. 477
15.2.8a.2 Receiver performance p. 477
15.2.8a.3 Mapping Filter Specifications p. 478
15.2.8a.4 Architecture Details p. 478
15.2.8a.4.1 The Hybrid Type 2 Architecture p. 478
15.2.8a.4.2 Traditional Type 1 Architecture p. 479
15.2.8a.5 Type 2 Operation Analysis p. 480
15.2.8a.5.1 Assumptions p. 480
15.2.8a.5.2 No Maximum Output power Reduction p. 480
15.2.8a.5.3 No Change in PA Capabilities p. 481
15.2.8a.5.4 Power Back Off based on Duplexer Power Tolerance p. 482
15.2.8a.6 Type 1 Operation - Comparison with Legacy Terminals p. 482
15.2.8a.6.1 Transmitter Path p. 482
15.2.8a.6.2 Receiver Path p. 482
15.2.8a.7 Type 1 Operation - Comparison with Legacy Terminals Using a Modified Hybrid Architecture p. 482
15.2.8a.8 Summary p. 483
15.2.9 Areas for Further Study p. 484
15.3 References p. 484
A Plots for clause 7 (dual-carrier and multi-carrier) p. 487
B Chapter 8 Link simulation results p. 489
B.1 Link performance for 8-PSK and 16 QAM with and without turbo coding p. 489
B.2 C/I-distribution p. 493
B.3 Link performance 32QAM p. 494
C Chapter 8 Link simulation results p. 497
C.1 Detailed link performance results p. 497
C.2 Detailed modulation detection performance results p. 501
D Chapter 8 Link simulation results p. 509
E Detailed simulation results for reduced transmission time interval (subclause 10.3.2) p. 512
F Flow-graphs of SMTP and POP3 scenarios (subclause 10.3.3) p. 514
$ Change history p. 517
